Scannable dynamic circuit latch

ABSTRACT

A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate series latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.

BACKGROUND

1. Field of the Invention

Embodiments of this invention relate generally to the field of latches, and more specifically to latches well-suited to use with domino circuits.

2. Related Art

In high-speed integrated circuit (IC) applications, particularly microprocessors and microcontrollers, Domino circuits are used, where appropriate, to provide speed advantages over static logic. Such applications rarely include scannable latches for similar reasons, e.g., the inclusion of a scannable latch inserts substantial delay into the circuit. In order to provide full scan support, a circuit includes static latches twice per cycle, and the clocks are shut down twice per cycle, in order to avoid conflicts. While scannable latches are desirable, in order to allow for improved logic testing than is otherwise possible, the delay imposed is too significant.

SUMMARY

A dynamic circuit latch, having the functionality of a domino circuit and a transparent latch, without the delay associated with the inclusion of a separate latch element. Embodiments include a fast scannable footed Domino dyanmic latch. Also described is a fast scannable delay reset Domino dynamic latch. A fast scannable compound Domino dynamic latch is also described.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention:

FIG. 1 is a block diagram of a dynamic circuit latch, in accordance with one embodiment of the present invention.

FIG. 2 is a block diagram of a dynamic circuit latch, including a footed domino circuit, in accordance with one embodiment of the present invention.

FIG. 3 is a block diagram of a dynamic circuit latch, including a delay reset domino circuit, in accordance with one embodiment of the present invention.

FIG. 4 is a block diagram of a dynamic circuit latch, including a compound domino circuit, in accordance with one embodiment of the present invention.

FIG. 5 is a block diagram of a dynamic circuit latch, including a series of inverters, in accordance with one embodiment of the present invention.

FIG. 6 is a block diagram of a dynamic circuit latch, including a fully scannable latch, in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

Scannable dynamic circuit latches are described. Reference will now be made in detail to several embodiments of the invention. While the invention will be described in conjunction with the alternative embodiment(s), it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternative, modifications, and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims.

Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one skilled in the art that the present invention may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

With reference to FIG. 1, a block diagram of a dynamic circuit latch 100 is depicted, in accordance with one embodiment of the invention. Dynamic circuit latch 100 has a domino component 110, which receives a clock signal 101 and an input signal 103, and produces an output signal 111. Domino component 110, in one embodiment, is a standard domino circuit with a slight modification. Any existing domino circuit can be improved through application of embodiments of the present invention; several specific embodiments are described below, with reference to FIGS. 2, 3, and 4. Dynamic circuit latch 100 also has a state component 150. State component 150 provides latching functionality for dynamic circuit latch 100. In one embodiment, described below with reference to FIG. 5, state component 150 functions as a transparent latch. In another embodiment, described below with reference to FIG. 6, state component 150 functions as a transparent latch while providing full scan support.

In operation, in one embodiment, dynamic circuit latch 100 acts as a combination of a domino circuit and a latch. The combination of domino component 110 and state component 150 provides both the blocking functionality of a latch, in that further inputs are prevented from affecting the present output, and the holding functionality, in that the previous state is retained at the output after the clock falls. However, dynamic circuit latch 100 imposes delay very similar to a standard domino circuit. As detailed below, the modifications made to the standard domino circuit in order to implement the embodiments of the present invention add very little delay, while the inclusion of state component 150, a side-load parasitic element, is much more efficient, in terms of delay, than including a separate series latch stage. The result is a single circuit with the functionality of both a domino circuit and a separate latch, which is free of the delay normally imposed by the latch.

With reference now to FIG. 2, a block diagram of a dynamic circuit latch 200 is depicted, in accordance with one embodiment of the present invention. Dynamic circuit latch 200 includes a domino component 210 and a state component 250. In this embodiment, Domino component 210 is a modified form of a standard footed domino circuit. Domino component 210 includes a precharge device 211, shown as a p-channel metal-oxide semiconductor field effect transistor (PFET), a logic block 215, implementing a combinational function f, a foot device 213 to cut off input, shown as a n-channel metal-oxide semiconductor field effect transistor (NFET), a half-latch keeper 217, and an output buffer 219, with a PFET 225 and an NFET 223. It should be appreciated that unlike most footed domino circuits, Domino component 210 includes a clock input 221 to output buffer 219, the importance of which is discussed below.

In operation, in one embodiment, when clock signal 201 is high, Dynamic circuit latch 200 operates as an ordinary footed domino circuit. Clock element 221 is in the precharge path, not the evaluation path, and so does not cause functional delay. Some small delay penalty is introduced by the parasitic side-load of state component 250. Any additional delay incurred is substantially less than that caused by inclusion of a separate latch element. When clock signal 201 is low, foot device 213 cuts off input, precharge device 211 pulls up, and Domino component 210 goes into precharge. On output buffer 219, NFET 223 is shut off, and output buffer 219 cannot pull down. Further, the internal node is precharged, so PFET 225 is off, and output buffer 219 cannot pull up. As a result, Domino component 210 is in tristate, and the output state can be held by state component 250. Dynamic circuit latch 200 is functionally equivalent to a footed domino circuit followed by a transparent latch, but without the delay associated with the inclusion of a separate series latch element.

With reference now to FIG. 3, a block diagram of a dynamic circuit latch 300 is depicted, in accordance with one embodiment of the present invention. Dynamic circuit latch 300 includes a domino component 310 and a state component 350. In this embodiment, Domino component 310 is a modified form of a standard delay reset domino circuit. Domino component 310 includes a precharge device 311, shown as a p-channel metal-oxide semiconductor field effect transistor (PFET), a logic block 315, implementing a combinational function f, a half-latch keeper 317, and an output buffer 319, with a PFET 325 and an NFET 323. It should be appreciated that unlike most delay reset domino circuits, Domino component 310 includes a clock input 321 to output buffer 319, the importance of which is discussed below.

In operation, in one embodiment, Dynamic circuit latch 300 operates much like Dynamic circuit latch 200, described above with reference to FIG. 2. When clock signal 301 is high, Dynamic circuit latch 300 operates as an ordinary delay reset domino circuit. Clock element 321 is in the precharge path, not the evaluation path, and so does not cause functional delay. Some small delay penalty is introduced by the parasitic side-load of state component 350. Again, any additional delay incurred is substantially less than that caused by inclusion of a separate series latch element.

Unlike Domino component 210, above, Domino component 310 lacks a foot device to cut off input. In order to ensure that Dynamic circuit latch 300 goes into tristate, the normal rules for placement of a delay reset domino circuit must be enforced e.g., a delay reset domino circuit must always follow a footed circuit, in order to ensure that the delay reset domino circuit will be able to precharge. That constraint aside, however, Domino component 310 operates similarly to Domino component 210, above. When clock signal 301 is low, precharge device 311 pulls up, and Domino component 310 goes into precharge. On output buffer 319, NFET 323 is shut off, and output buffer 319 cannot pull down. Further, the internal node is precharged, so PFET 325 is off, and output buffer 319 cannot pull up. As a result, Domino component 310 is in tristate, and the output state can be held by state component 350. Dynamic circuit latch 300 is functionally equivalent to a delay reset domino circuit followed by a transparent latch, but without the delay associated with the inclusion of a separate series latch element.

With reference now to FIG. 4, a block diagram of a dynamic circuit latch 400 is depicted, in accordance with one embodiment of the present invention. Dynamic circuit latch 400 includes a domino component 410 and a state component 450. In this embodiment, Domino component 410 is a modified form of a standard compound domino circuit. Domino component 410 includes several precharge devices 411 a and 411 b, shown as p-channel metal-oxide semiconductor field effect transistors (PFETs), several logic blocks 415 a and 415 b, for implementing combinational functions, f and g, several half-latch keepers 417 a and 417 b, and an output buffer 419. It should be appreciated that unlike most compound domino circuits, Domino component 410 includes a clock input 421 to output buffer 419, the importance of which is discussed below.

In operation, in one embodiment, Dynamic circuit latch 400 operates much like Dynamic circuit latch 300, described above with reference to FIG. 3. When clock signal 401 is high, Dynamic circuit latch 400 operates as an ordinary delay reset domino circuit. Clock element 421 is in the precharge path, not the evaluation path, and so does not cause functional delay. Some small delay penalty is introduced by the parasitic side-load of state component 450. Again, any additional delay incurred is substantially less than that caused by inclusion of a separate series latch element.

Domino component 410 differs from Domino component 310 in two important aspects. First, Domino component 410 allows for multiple logic blocks 415 a and 415 b, as per a normal compound domino circuit, meaning several logical operations can be performed within the circuit to produce output. Second, output buffer 419 is substantially different from output buffer 319. Output buffer 419 is a standard NAND gate, with the addition of clock input 421. Otherwise, operation of Domino component 410 is similar to that of Domino component 310. In this embodiment, Domino component 410 also lacks a foot device to cut off input. In order to ensure that Dynamic circuit latch 400 goes into tristate, the normal rules for placement of a delay reset compound domino circuit must be enforced, e.g., a delay reset compound domino circuit must always follow a footed circuit, in order to ensure that the delay reset compound domino circuit will be able to precharge. In another embodiment, Domino component 410 is implemented to include a plurality of foot devices, similar to foot device 213. When clock signal 401 is low, precharge device 411 pulls up, and Domino component 410 goes into precharge. Domino component 410 is put into in tristate, and the output state can be held by state component 450. Dynamic circuit latch 400 is functionally equivalent to a delay reset compound domino circuit followed by a transparent latch, but without the delay associated with the inclusion of a separate series latch element.

With reference now to FIG. 5, a block diagram of a dynamic circuit latch 500 is depicted, in accordance with one embodiment of the present invention. Dynamic circuit latch 500 includes a domino component 510 and a state component 550. Domino component 510 receives clock signal 501 and data signal 503 as inputs. Domino component 510 can be implemented, in several embodiments, as domino component 210, domino component 310, or domino component 410. When domino component 210 is used in conjunction with dynamic circuit 500, a dynamic footed domino circuit is described. When domino component 310 is used in conjunction with dynamic circuit 500, a dynamic delay reset domino circuit is described. When domino component 410 is used in conjunction with dynamic circuit 500, a dynamic compound domino circuit is described. In this embodiment, state component 550 is shown as a simple pair of inverters. This implementation, coupled with domino component 510, provides the functionality of a domino circuit followed by a transparent (non-scannable) latch.

With reference now to FIG. 6, a block diagram of a dynamic circuit latch 600 is depicted, in accordance with one embodiment of the present invention. Dynamic circuit latch 600 includes a domino component 610 and a state component 650. Domino component 610 receives clock signal 601 and data signal 603 as inputs. Domino component 610 can be implemented, in several embodiments, as domino component 210, domino component 310, or domino component 410. When domino component 210 is used in conjunction with dynamic circuit 600, a scannable dynamic footed domino circuit is described. When domino component 310 is used in conjunction with dynamic circuit 600, a scannable dynamic delay reset domino circuit is described. When domino component 410 is used in conjunction with dynamic circuit 600, a scannable dynamic compound domino circuit is described. In this embodiment, state component 650 includes a pair of feedback inverters, first inverter 655 and second inverter 660, implemented as two tristate buffers. One embodiment also includes a slave latch 680, to allow the state of the output to be read at any time.

In operation, state component 650 provides full scanning and latching functionality for dynamic circuit latch 600. Scan-in and scan-out are shown as sin and sout, respectively. First inverter 655 is controlled by a separate scan clock, scan phase one signal (sph1) 651 and scan phase one bar (sph1_b). Second inverter 660 is clocked by the functional clock, clock signal 601 (Φ and Φb), such that when clock signal 601 is high, second inverter 660 goes into tristate, which minimizes the side load caused by state component 650, allowing dynamic circuit latch 600 to function as a normal domino circuit of a given type. When clock signal 601 is low, and scan is inhibited, first inverter 655 is activated, second inverter 660 is conducting, and the output state is held. When the scan clock is enabled, the held state can be overridden, and a scan-in value can be forced into the latch.

At any time, slave latch 680 can be used to monitor the state of state component 650 via the scan-out port, whether dynamic circuit latch 600 is in functional mode or in scan mode. Slave latch 680 is activated by a second set of scan clock signals.

The inclusion of state component 650 in dynamic circuit latch 600 allows for transparent latch functionality as well as full scan capability, while not incurring the delay that would result from including a separate series latch element behind a traditional domino circuit.

Again, it is appreciated that the discussion above is intended to be illustrative of several embodiments of the present invention. Other embodiments are possible, and will be apparent to one skilled in the art. Moreover, combinations of the above exemplary embodiments are desirable, and while not specifically enumerated herein, are intended as part of the present invention.

Embodiments of the present invention described above thus relate to a scannable dynamic circuit latch. While the present invention has been described in particular exemplary embodiments, the present invention should not be construed as limited by such embodiments, but rather construed according to the following claims and their equivalents. 

1. A dynamic circuit latch comprising: a domino component, for receiving a clock signal and an input signal, and for producing an output; and a state component, coupled to said domino component, for retaining said output, wherein said domino component and said state component are configured to assume a tristate when induced by said clock signal, such that said output is held at said state component, and wherein said input signal cannot alter said output while so held.
 2. The dynamic circuit latch of claim 1 free of the delay imposed by inclusion of a separate series latch circuit.
 3. The dynamic circuit latch of claim 1, wherein said state component comprises: a first tristate buffer; and a second tristate buffer coupled to said first tristate buffer, wherein said first tristate buffer and said second tristate buffer are configured to function as an exposed, scannable latch when said domino component is in said tristate condition.
 4. The dynamic circuit latch of claim 3, further comprising: a slave latch assembly, coupled to said second tristate buffer, and configured to allow monitoring of said output.
 5. The dynamic circuit latch of claim 1, wherein said domino component comprises: a precharge component, for precharging said domino component; a function component, coupled to said precharge component, for performing a function with said input signal and producing said output; a keeper component, coupled to said precharge component, for holding said output from said function component; and an output component, coupled to said precharge component, for holding said output.
 6. The dynamic circuit latch of claim 5, wherein said domino component further comprises: a foot component, coupled to said precharge component, for cutting off said input signal when induced by said clock signal.
 7. The dynamic circuit latch of claim 1, wherein said domino component comprises: a plurality of precharge components; a plurality of function components, coupled to said plurality of precharge components, for performing a plurality of functions and producing a plurality of outputs; a plurality of keeper components, coupled to said plurality of precharge components, for holding said plurality of outputs; and an output component, coupled to said plurality of precharge components, for holding said output.
 8. A scannable latch circuit comprising: a domino circuit comprising a data input port for receiving an input data signal and a clock input port for receiving a clock input wherein said domino circuit is operable to generate an output signal over an output port; and a scannable state circuit coupled to said output port, wherein said scannable state circuit, in a first clock mode, is operable to hold a signal state of said output port and, wherein further, signal transitions at said input port do not alter said signal state.
 9. A scannable latch circuit as described in claim 8 wherein said scannable state circuit comprises a scan-in port and a scan-out port.
 10. A scannable latch circuit as described in claim 9 wherein said scannable state circuit further comprises a scan clock input.
 11. A scannable latch circuit as described in claim 10 wherein said domino circuit comprises a footed domino circuit.
 12. A scannable latch circuit as described in claim 10 wherein said domino circuit comprises a delay reset domino circuit.
 13. A scannable latch circuit as described in claim 10 wherein said domino circuit comprises a compound domino circuit.
 14. A scannable latch circuit as described in claim 8 wherein said domino circuit further comprises: a precharge subcircuit; a keeper subcircuit coupled to said precharge subcircuit; and an output buffer subcircuit coupled to said keeper subcircuit and coupled to said precharge subcircuit wherein said output buffer subcircuit is for generating said output signal.
 15. A scannable latch circuit as described in claim 14 wherein said scannable state circuit further comprises: a first tri-state buffer circuit coupled to a scan-in port and coupled to said output port; a second tri-state buffer circuit coupled to said first tri-state buffer circuit and coupled to said output port; and a scan-out read circuit coupled to said second tri-state buffer circuit and coupled to a scan-out port.
 16. A scannable latch circuit as described in claim 8 wherein said scannable state circuit further comprises: a first tri-state buffer circuit coupled to a scan-in port; a second tri-state buffer circuit coupled to said first tri-state buffer circuit; and a scan-out read circuit coupled to said second tri-state buffer circuit and coupled to a scan-out port.
 17. A dynamic circuit latch, comprising: a domino component having a clock port to receive a clock signal and an input port to receive an input signal, wherein said domino component is operable in a first clock state to produce an output at an output port, and wherein said domino component is operable in a second clock state to prevent said input from affecting said output; and a state component coupled to said output port, wherein said state component is operable in said first clock state to inhibit conduction through said state component, and wherein said state component is operable in a second clock state to hold said output.
 18. The dynamic circuit latch of claim 17 wherein said domino component comprises a footed domino circuit.
 19. The dynamic circuit latch of claim 17 wherein said domino circuit comprises a delay reset domino circuit.
 20. The dynamic circuit latch of claim 17 wherein said domino circuit comprises a compound domino circuit.
 21. The dynamic circuit latch of claim 20 wherein said compound domino circuit comprises a footed compound domino circuit.
 22. The dynamic circuit latch of claim 20 wherein said compound domino circuit comprises a delay resetcompound domino circuit.
 23. The dynamic circuit latch of claim 17 wherein said state element comprises: a scan-in read circuit coupled to a scan-in port and coupled to said output port; and a scan-out read circuit coupled to said scan-in read circuit and coupled to a scan-out port for outputting a held value.
 24. The dynamic circuit latch of claim 21 wherein said state element further comprises: a first tristate buffer circuit coupled to said scan-in port and coupled to a scan-clock input port; and a second tristate buffer circuit coupled to said first tristate buffer and coupled to a functional clock input port.
 25. The dynamic circuit latch of claim 24 wherein said state element further comprises: a scan-out read circuit coupled to said second tristate buffer circuit and coupled to said scan-out port.
 26. The dynamic circuit latch of claim 17 wherein said domino component further comprises: a precharge subcircuit; a keeper subcircuit coupled to said precharge subcircuit; and an output buffer subcircuit coupled to said keeper subcircuit and coupled to said precharge subcircuit wherein said output buffer subcircuit is for generating said output signal.
 27. The dynamic circuit latch of claim 26 wherein said state component further comprises: a first tristate buffer circuit coupled to a scan-in port and coupled to said output port; a second tristate buffer circuit coupled to said first tristate buffer circuit and coupled to said output port; and a scan-out read circuit coupled to said second tristate buffer circuit and coupled to a scan-out port. 